Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability

Very Low Power Neural Network FPGA Accelerators for Tag-Less Remote Person Identification Using Capacitive Sensors

Human detection, identification, and monitoring are essential for many applications aiming to make smarter the indoor environments, where most people spend much of their time (like home, office, transportation, or public spaces). The capacitive sensors can meet stringent privacy, power, cost, and unobtrusiveness requirements, they do not rely on wearables or specific human interactions, but they may need significant on-board data processing to increase their performance. We comparatively analyze in terms of overall processing time and energy several data processing implementations of multilayer perceptron neural networks (NNs) on board capacitive sensors. The NN architecture, optimized using augmented experimental data, consists of six 17-bit inputs, two hidden layers with eight neurons each, and one four-bit output. For the software (SW) NN implementation, we use two STMicroelectronics STM32 low-power ARM microcontrollers (MCUs): one MCU optimized for power and one for performance. For hardware (HW) implementations, we use four ultralow-power field-programmable gate arrays (FPGAs), with different sizes, dedicated computation blocks, and data communication interfaces (one FPGA from the Lattice iCE40 family and three FPGAs from the Microsemi IGLOO family). Our shortest SW implementation latency is 54.4 µs and the lowest energy per inference is 990 nJ, while the shortest HW implementation latency is 1.99 µs and the lowest energy is 39 nJ (including the data transfer between MCU and FPGA). The FPGAs active power ranges between 6.24 and 34.7 mW, while their static power is between 79 and 277 µW. They compare very favorably with the static power consumption of Xilinx and Altera low-power device families, which is around 40 mW. The experimental results show that NN inferences offloaded to external FPGAs have lower latency and energy than SW ones (even when using HW multipliers), and the FPGAs with dedicated computational blocks (multiply-accumulate) perform best

Role of dispersant and humidity on the setting of millimetric films of aluminous cement prepared by tape casting

An aluminous cement (Secar 71 from Lafarge) has been used for preparing millimetre thick films by tape casting. Slurry preparation is described. The effect of several dispersants has been studied. The optimum dispersion, associated with the minimum viscosity, is obtained with minimal amounts of dispersant in the case of acetic and propionic acids. Indeed, the corresponding quantities of dispersant are less than 0.5% by weight relative to cement. In addition to its dispersive role, acetic acid plays a role in the setting. It has a retarding effect below 1% by weight relative to the mass of cement and from this amount, it plays an accelerating role on setting. Tapes prepared with cement, water, acetic acid, PEG 300 have been left to set in different environments at 20 ◦C (50% or 95% relative humidity, water). The formation of aluminous calcium hydrates is most important when setting is done in water. Lastly, the advantage of setting in water is also discussed with respect to the elimination of the different organic products that have been used for tape casting

Calcium aluminate cement tapes - Part I: Structural and microstructural characterizations

International audienceThis present paper concerns the structural and microstructural characterization of 1 mm thick calcium aluminate cement tapes prepared by tape casting. A study of the effect of environment, time and the consolidation temperature on the structural properties and microstructure has been undertaken. Consolidation environments studied are air, water and an environment saturated in humidity for storage durations of 1, 4 or 30 days at a temperature of 20 or 70 °C. The structural characterization was carried out using XRD. The microstructural characterization was carried out through the distribution of pore volume by mercury porosimetry measurements and SEM micrographs. The effects of the various consolidation parameters were compared and discussed. The tape consolidated for 30 days in water at 70 °C has the most advanced hydration with the formation of stable hydrates. This is evidenced by the reduction of the inter-granular pore size and the microstructure densification

Calcium aluminate cement tapes - Part II: Physical properties

International audienceTape casting is a process often used for the preparation of microelectronics substrates. The present work is a continuation of the first part where we have discussed the structural and microstructural characteristics of calcium aluminate cement tape. Indeed, in this second part, we focus on the physical properties of these tapes such as electrical, thermal, mechanical characterizations and surface roughness. We studied in particular how these physical properties vary according to the setting environment (water, air at 50% relative humidity or air saturated in humidity), setting time (1 day, 4 days or 1 month) and setting temperature (20 °C or 70 °C in the case of water setting environment). A Heat treatment on the consolidated tape was made essentially to decrease the dielectric constant. Following our results and comparing the physical properties with those of substrates commonly used in microelectronics, in particular alumina substrates, our films can be potentially used as microelectronics substrate

A comparative study of the thermal behaviour of phosphate washing sludge from Tunisia and Morocco

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Effect of temperature and clay addition on the thermal behavior of phosphate sludge

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